module gpr_tb;
  reg clk, rst;
  reg RegWr;
  reg [31:0]busW;
  reg [4:0]ra, rb, rw;

  wire [31:0]busA, busB, Data_in;

  gpr gpr_dut (
    .clk(clk),
    .rst(rst),
    .RegWr(RegWr),
    .busW(busW),
    .ra(ra),
    .rb(rb),
    .rw(rw),
    .busA(busA),
    .busB(busB),
    .Data_in(Data_in)
  );

  // 初始化模块输入
  initial begin
    clk = 0;   
    repeat (8) begin           //8个周期
      #5 clk = ~clk;
    end
  end
  
  initial begin
    rst = 1;
    #1 rst = 0;

    RegWr = 0;
    busW = 32'h12345678;
    ra = 5;
    rb = 10;
    rw = 15;
  end

  initial begin
    $dumpfile("gprwave.vcd");
    $dumpvars(0,gpr_tb);
  end
  
  // 模拟gpr模块的操作
  always @(posedge clk) begin
    RegWr = 1;             //寄存器堆写使能
    busW = $random;        //写入值取随机数
    ra = 15;
    rb = 20;
    rw = 25;
  end
  
endmodule
